GROMACS

In order to have fast asynchronous transfers between host and CUDA GPUs, host memory buffers need to be page-locked (aligned with the memory page size + exposed to CUDA via cudaHostRegister() function).
There is a crude hack for PME GPU purposes, which aligns existing coordinates, charges and forces buffers: https://gerrit.gromacs.org/#/c/6578
There is also a tangent work by Mark: https://gerrit.gromacs.org/#/c/6552
No matter which code we would use, the important questions are whether and how we would want to use page-aligned memory conditionally (e.g. based on PME running on CPU/GPU), and could we face problems/limits otherwise
(consider a dozen of ranks each using a dozen of page-aligned buffers with whatever large page size).
One long-term solution would be having a page-locked memory provider object which would minimize the paged memory use.